JPH0438141B2 - - Google Patents
Info
- Publication number
- JPH0438141B2 JPH0438141B2 JP59011234A JP1123484A JPH0438141B2 JP H0438141 B2 JPH0438141 B2 JP H0438141B2 JP 59011234 A JP59011234 A JP 59011234A JP 1123484 A JP1123484 A JP 1123484A JP H0438141 B2 JPH0438141 B2 JP H0438141B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- layer
- silicon
- type
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011234A JPS60154549A (ja) | 1984-01-24 | 1984-01-24 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011234A JPS60154549A (ja) | 1984-01-24 | 1984-01-24 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60154549A JPS60154549A (ja) | 1985-08-14 |
| JPH0438141B2 true JPH0438141B2 (en]) | 1992-06-23 |
Family
ID=11772245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59011234A Granted JPS60154549A (ja) | 1984-01-24 | 1984-01-24 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154549A (en]) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63119578A (ja) * | 1986-11-07 | 1988-05-24 | Seiko Epson Corp | 半導体装置 |
| JPH01264254A (ja) * | 1988-04-15 | 1989-10-20 | Agency Of Ind Science & Technol | 積層型半導体装置の製造方法 |
| US5643801A (en) | 1992-11-06 | 1997-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Laser processing method and alignment |
| US6908797B2 (en) | 2002-07-09 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| JP2004048029A (ja) * | 2002-07-09 | 2004-02-12 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US6821826B1 (en) * | 2003-09-30 | 2004-11-23 | International Business Machines Corporation | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers |
| US7041576B2 (en) * | 2004-05-28 | 2006-05-09 | Freescale Semiconductor, Inc. | Separately strained N-channel and P-channel transistors |
| US8232598B2 (en) * | 2007-09-20 | 2012-07-31 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
| KR101930730B1 (ko) * | 2009-10-30 | 2018-12-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| WO2011070905A1 (en) * | 2009-12-11 | 2011-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile latch circuit and logic circuit, and semiconductor device using the same |
-
1984
- 1984-01-24 JP JP59011234A patent/JPS60154549A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60154549A (ja) | 1985-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4651408A (en) | Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies | |
| JP2923700B2 (ja) | 半導体装置およびその作製方法 | |
| US4768076A (en) | Recrystallized CMOS with different crystal planes | |
| KR101186291B1 (ko) | 게르마늄 온 인슐레이터 구조 및 이를 이용한 반도체 소자 | |
| JPH0438141B2 (en]) | ||
| JPH0438140B2 (en]) | ||
| JPH0325949B2 (en]) | ||
| JPH01264254A (ja) | 積層型半導体装置の製造方法 | |
| US4695856A (en) | Semiconductor device | |
| JPH0236056B2 (ja) | Handotaisochinoseizohoho | |
| JPH02194561A (ja) | 薄膜半導体装置とその製造方法 | |
| JPS5893216A (ja) | 半導体装置の製造方法 | |
| JPH04233758A (ja) | 半導体装置とその製造方法 | |
| JPS597231B2 (ja) | 絶縁ゲイト型電界効果半導体装置の作製方法 | |
| JPH0530075B2 (en]) | ||
| JPS59220972A (ja) | Ｍｏｓ形半導体装置およびその製造方法 | |
| JPS63226070A (ja) | Ｍｉｓトランジスタ | |
| JPH0517701B2 (en]) | ||
| JPS60113452A (ja) | 半導体装置およびその製造方法 | |
| JPS60152066A (ja) | 電界効果型トランジスタ | |
| JPH0536911A (ja) | ３次元回路素子およびその製造方法 | |
| JPS5837952A (ja) | 半導体装置およびその製造方法 | |
| JPS6236855A (ja) | 半導体装置の製造方法 | |
| JP2515040B2 (ja) | 半導体装置およびその製造方法 | |
| JPS62181455A (ja) | 半導体装置の製造方法 |